In U.S. Pat. No. 4,178,614 to Sauer, an arrangement for shifting charge packets is disclosed. In this approach, two parallel register arrays (A and B) and a serial register (C) are used to perform the desired readout function. Register A is an area imager CCD having an array of rows and columns of electrodes used to integrate charge employing one electrode to store a charge packet and a second electrode to act as a barrier to isolate the charge from an adjacent charge packet area imager. In each column there are assigned two electrodes per charge packet. The configuration of the array is such that all packets found in each row (or line) of the array are managed and controlled together at once. At the end of the charge integration period, a four electrode per charge packet transfer technique between registers A and B is used to shift the packets to an identical storage register B. In register B, the four electrode per packet transfer technique is converted back to a two electrode storage arrangement as was employed during the register A integration mode. Storage register B is then read into a serial register C, again using a four electrode per packet transfer technique, and subsequently shifted out of the device while register A begins its next integration phase. Generation of the clocking schemes for shifting charge packets from register A to register B and from register B to register C is by use of transistor or CCD shift registers. An example given in the Sauer patent, in column 4, line 53, is the RCA CD4062 200-stage dynamic shift register. The patent indicates that the shifting or transferring of charge packets requires a data clock, two shift clocks (one each for register A and B) and a fourth clock for use in switching between clocking charge packets from register A to register B, or integration of charge in register A.
A paper was written by A. J. P. Theuwissen, C. H. L. Weijtens, L. J. M. Esser, J. N. G. Cox, H. T. A. R. Cuyvelaar and W. C. Keur at the 1984 IEDM conference entitled "The According Imager: An Ultra high Density Frame Transfer CCD." This paper described a method to transfer charge packets using a CCD readout scheme similar to the patent described above. Specifically, the paper discusses a three CCD register device including an image sensor having an array of electrodes, an identical storage array and a serial readout register. Two electrodes in each column are used to collect integrated charge packets. Clocking or readout of the two parallel register arrays is via a dynamic, on chip clock generator using two data clocks and two shifting clocks for each of the two array for a total of 6 clocks. The dynamic shift register consists of a series of CMOS inverters separated by a pass through transistor which, when operated as described, generates the necessary clocking function for reading out the charge packets. During readout, four electrodes per charge packet are used during readout.
The object of this invention is to (1) reduce the number of clocks required to shift the integrated charge to the serial readout register C to a minimum, thus reducing the complexity of the logic timing used to perform the required shifting functions; and (2) eliminate register B thus conserving silicon area (which is very costly) and reducing the number of charge transfers (which degrades performance). The elimination of register B would also reduce the exposure of charge packets to undesired intrinsic charge generation sources corrupting the signal.